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Changes in OHCI 1.1

InitialBandwidthAvailable, InitialChannelsAvailableHi/Lo
miniROM
BIBimageValid
atomic Configuration ROM updates: A write to 5.5.6 ConfigurationROMmapping is stored into a ConfigurationROMmappingNext shadow register and does not take immediate effect on ConfigurationROMmapping and the Configuration ROM physical DMA itself. At the next bus reset, the controller updates ConfigurationROMmapping by ConfigurationROMmappingNext and loads 5.5.2 ConfigROMheader and 5.5.4 BusOptions from system memory at ConfigurationROMmapping.
ackTardyEnable and ack_tardy interrupt
tag1SyncFilterLock
regAccessFail interrupt on register accesses when SCLK is inactive despite LPS=1
(The spec says that controllers must not generate PCI target aborts in this case, but some do.)
softInterrupt
selfIDcomplete2
for all context types:
- For stopped (run=0,active=0) contexts, CommandPtr can also point to the next descriptor, not only to the last one.
- For running (run=1,active=1) contexts, CommandPtr is no longer unspecified but can point to either the current or to the next descriptor.
asynchronous transmit contexts:
- out-of-order AT pipelining
isochronous transmit contexts:
- evt_underrun is no longer possible.
- When running (run=1,active=1), CommandPtr always points to the current descriptor.
- Descriptors with skipAddress now have the interrupt field to get notifications for skipping.
- On skip processing overflow, status evt_timeout.
isochronous receive contexts:
- dual-buffer mode
PCI power management

speeds higher than S400
betaFrame bits in descriptors and xferStatus
Software can clear the LPS bit.
physReqDebug
PhysicalSplitTimeout
asynchronous transmit contexts:
- On a bus reset, the controller is not required to flush the AT queue.

The 1.2 revision was never finished. This list may be incomplete, and it is unknown how much of this is implemented in hardware.